The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2026

Filed:

Jul. 26, 2023
Applicant:

Vanguard International Semiconductor Corporation, Hsinchu, TW;

Inventors:

Chen-Dong Tzou, Taipei City, TW;

Wei-Chih Cheng, Tainan City, TW;

Chia-Hao Lee, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/47 (2025.01); H10D 30/01 (2025.01); H10D 62/85 (2025.01); H10D 64/00 (2025.01); H10D 64/01 (2025.01);
U.S. Cl.
CPC ...
H10D 64/112 (2025.01); H10D 30/015 (2025.01); H10D 30/475 (2025.01); H10D 62/8503 (2025.01); H10D 64/01 (2025.01);
Abstract

A high electron mobility transistor includes a semiconductor channel layer and a semiconductor barrier layer disposed on a substrate in sequence. A source electrode and a drain electrode are disposed on the semiconductor channel layer. A semiconductor cap layer is disposed on the semiconductor barrier layer. A first dielectric layer is disposed over the source electrode, the semiconductor cap layer and the drain electrode. A first via passes through the first dielectric layer and is extended downward onto the semiconductor cap layer. A gate electrode is disposed on the first dielectric layer and in contact with the first via. A first field plate is disposed in the first dielectric layer. A second field plate is disposed on the first dielectric layer and in contact with the first field plate.


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