The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2026

Filed:

Sep. 11, 2023
Applicant:

Ideal Semiconductor Devices, Inc., Bethlehem, PA (US);

Inventors:

David Jauregui, Bethlehem, PA (US);

Stanislav Soloviev, Breinigsville, PA (US);

Philip Rutter, Bethlehem, PA (US);

Assignee:

IDEAL SEMICONDUCTOR DEVICES, INC., Bethlehem, PA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 62/10 (2025.01); H10W 29/00 (2026.01); H10W 42/80 (2026.01);
U.S. Cl.
CPC ...
H10D 62/105 (2025.01); H10W 29/00 (2026.01); H10W 29/01 (2026.01); H10W 42/80 (2026.01);
Abstract

A semiconductor device is provided that includes an epitaxial layer disposed on a semiconductor substrate, the epitaxial layer including an active region, in which at least one active element is formed, and an edge termination region, in which at least one edge termination structure is formed, the edge termination region being laterally adjacent to the active region. The semiconductor device further includes a charged layer disposed on an upper surface of the epitaxial layer, the charged layer covering at least a portion of the active region and extending laterally over at least a portion of the edge termination region. Active trenches may be formed in the active region, and at least one edge trench may be formed in the edge termination region. The charged layer may be formed on sidewalls of each of the active trenches and the edge trench using atomic layer deposition in a same processing step.


Find Patent Forward Citations

Jauregui, David. (2026). Combined charge balance and edge termination surface passivation for a semiconductor device and methods of fabricating the same (U.S. Patent No. 12727209). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12727209

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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