The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2026

Filed:

Jun. 21, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Sheng-Fu Hsu, Hsinchu, TW;

Shih-Fan Chen, Hsinchu City, TW;

Chen-Yi Lee, Keelung City, TW;

Pin-Chen Chen, New Taipei City, TW;

Lin-Yu Huang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 10/60 (2025.01); H03K 17/081 (2006.01); H10D 10/01 (2025.01); H10D 62/10 (2025.01); H10D 64/00 (2025.01); H10D 89/60 (2025.01);
U.S. Cl.
CPC ...
H10D 10/60 (2025.01); H03K 17/08104 (2013.01); H03K 17/08112 (2013.01); H10D 10/061 (2025.01); H10D 62/107 (2025.01); H10D 62/115 (2025.01); H10D 62/124 (2025.01); H10D 64/112 (2025.01); H10D 89/711 (2025.01);
Abstract

A semiconductor device may include a electrostatic discharge (ESD) protection circuit and a high voltage ESD triggering circuit that is configured to trigger ESD protection for high voltage circuits of the semiconductor device. The high voltage ESD triggering circuit may be implemented by one or more of the example implementations of high voltage ESD triggering circuits described herein. The example implementations of high voltage ESD triggering circuits described herein are capable of handle high voltages of the high voltage circuits included in the semiconductor device. This reduces the likelihood of and/or prevents premature triggering of ESD protection during normal operation for these high voltage circuits, and enables the high voltage circuits to be protected from high voltage ESD events.


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