The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2026

Filed:

Feb. 22, 2023
Applicant:

Yangtze Memory Technologies Co., Ltd., Wuhan, CN;

Inventors:

Jin Yong Oh, Wuhan, CN;

Youn Cheul Kim, Wuhan, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 43/27 (2023.01); H10B 41/35 (2023.01); H10B 41/41 (2023.01); H10B 43/35 (2023.01); H10P 50/00 (2026.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H10B 41/35 (2023.02); H10B 41/41 (2023.02); H10B 43/35 (2023.02); H10P 50/73 (2026.01);
Abstract

A semiconductor device includes a first substrate, a second substrate, a first connection structure, and a second connection structure. A transistor is formed in a first side of the first substrate. A doped region is formed in a first side of the second substrate. The first connection structure is formed over a second side of the second substrate, and coupled to the doped region through a first VIA that extends from the second side of the second substrate to the doped region. The second connection structure is formed over the first side of the first substrate, connected with the first connection structure via a through silicon VIA, and coupled to the transistor through a bonding VIA. The first substrate is bonded to the second substrate by the bonding VIA, with the first side of the first substrate and the first side of the second substrate being facing each other.


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