Memory cell including dual-antifuse device, memory structure, and operating method

Abstract

Disclosed is a memory cell including a dual-antifuse device between a first pass-gate transistor and a second pass-gate transistor. The dual-antifuse device includes first and second antifuses having a common terminal and each also having an additional terminal opposite the common terminal. The first pass-gate transistor is connected between a first bitline and the additional terminal of the first pass-gate transistor. The second pass-gate transistor is connected between a second bitline and the additional terminal of the second pass-gate transistor. The common terminal of the first and second antifuses and gates of the first and second pass-gate transistors are connected to a wordline. Also disclosed is a memory structure including an array of such memory cells and an associated operating method. Within the array, different wordline and bitline bias conditions can be employed in order to reliably perform programming or read operations of a selected antifuse in a selected cell.