The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2026

Filed:

Sep. 06, 2024
Applicant:

Sandisk Technologies, Inc., Milpitas, CA (US);

Inventors:

Mark Kraman, San Jose, CA (US);

Kartik Sondhi, Milpitas, CA (US);

Peng Zhang, Fremont, CA (US);

Johann Alsmeier, San Jose, CA (US);

Senaka Kanakamedala, San Jose, CA (US);

Yan Li, Milpitas, CA (US);

Assignee:

Sandisk Technologies, Inc., Milpitas, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); H10B 41/20 (2023.01); H10B 41/27 (2023.01); H10B 41/50 (2023.01); H10B 43/10 (2023.01); H10B 43/20 (2023.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01); H10B 51/10 (2023.01); H10B 51/20 (2023.01); H10B 51/40 (2023.01); H10B 51/50 (2023.01); H10D 30/01 (2025.01); H10D 30/69 (2025.01); H10W 20/41 (2026.01); H10W 20/42 (2026.01);
U.S. Cl.
CPC ...
G11C 5/063 (2013.01); H10B 41/20 (2023.02); H10B 41/27 (2023.02); H10B 41/50 (2023.02); H10B 43/10 (2023.02); H10B 43/20 (2023.02); H10B 43/27 (2023.02); H10B 43/40 (2023.02); H10B 51/10 (2023.02); H10B 51/20 (2023.02); H10B 51/40 (2023.02); H10B 51/50 (2023.02); H10D 30/0415 (2025.01); H10D 30/701 (2025.01); H10W 20/42 (2026.01); H10W 20/435 (2026.01);
Abstract

A device structure includes base semiconductor rail structures overlying a semiconductor substrate, bottom bit lines contacting a sidewall of a respective one of the base semiconductor rail structures, a two-dimensional array of lower semiconductor pillars, lower gate electrode lines overlying the bottom bit lines and laterally spaced from sidewall segments of a respective column of the lower semiconductor pillars by a lower gate dielectric layer, a two-dimensional array of upper semiconductor pillars, upper gate electrode lines overlying the lower gate electrode lines and laterally spaced from sidewall segments of a respective column of the upper semiconductor pillars by an upper gate dielectric layer, and at least one top bit line contacting top surfaces of a respective row of upper semiconductor pillars.


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