Protocol including timing calibration between memory request and data transfer

Abstract

The described embodiments provide an integrated circuit (IC) memory controller to control operation of an IC memory device. The IC memory device includes a memory core and internal clock circuitry. The IC memory controller includes a command interface to transmit, to the IC memory device, a read command and a phase adjustment command. The phase adjustment command specifies a phase adjustment operation, to be performed by the IC memory device, in an intervening time between receipt of the read command by the IC memory device and the IC memory device outputting data accessed in response to receiving the read command. The internal clock circuitry is disabled after outputting the data. A data interface receives the data. A transmitter transmits a timing reference signal to the IC memory device to time outputting of the data by the IC memory device.