The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2026

Filed:

Mar. 31, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Joshua B. Fryman, Corvallis, OR (US);

Byoungchan Oh, Portland, OR (US);

Sai Dheeraj Polagani, Hillsboro, OR (US);

Kevin P. MA, Beaverton, OR (US);

Robert S. Pawlowski, Beaverton, OR (US);

Bharadwaj Coimbatore Krishnamurthy, Hillsboro, OR (US);

Shruti Sharma, Hillsboro, OR (US);

Smitha P. Vasantha Kumar, Hillsboro, OR (US);

Jason Howard, Portland, OR (US);

Daniel S. Klowden, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2018.01); G06F 11/34 (2006.01); G06F 15/80 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3851 (2013.01); G06F 11/3409 (2013.01);
Abstract

A system is provided that includes a set of graph processing cores and a set of dense compute cores, where the set of graph processing cores and the set of dense cores are interconnected in a network. The dense compute cores include offload queue circuitry to receive an offload request from the set of graph processing cores to handle dense compute workloads. Memory controllers are also provided in the system for use by the graph processing cores in reading and writing to memory in association with sparse graph applications, the memory controllers enhanced to efficiently handle memory transactions in sparse graph applications.


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