The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2026

Filed:

Jul. 03, 2024
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Marcos Alvarez Gonzalez, Munich, DE;

Andrea Sorrentino, Munich, DE;

Morshed Mohammed, Freising, DE;

Luiza Souza Correa, Munich, DE;

Wolfgang Anton Spirkl, Germering, DE;

Paritosh Piyush Sahu, Munich, DE;

Martin Bach, Munich, DE;

Ronny Schneider, Höhenkirchen-Siegertsbrunn, DE;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/12 (2006.01); G06F 1/10 (2006.01); G06F 1/3203 (2019.01);
U.S. Cl.
CPC ...
G06F 1/10 (2013.01); G06F 1/3203 (2013.01);
Abstract

Methods, systems, and devices for techniques for coupled host and memory dies are described. As part of a low-speed testing phase of a memory system, a low-speed tester may measure the change in phase of a set of clock signals in response to a change in a configuration of the memory system. For example, the low-speed tester may communicate with a mimic circuit of the memory system to determine a first frequency of a first clock signal of the multi-phase clock associated with a first configuration of the memory system and determine a second frequency of the first clock signal associated with a second configuration of the memory system. The low-speed tester may store an indication of the difference between the first frequency and the second frequency, and a high-speed tester may use the difference as part of selecting a set of trim parameters for the multi-phase clock signal.


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