The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2026

Filed:

Jan. 09, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Ming-Fa Chen, Taichung City, TW;

Yun-Han Lee, Baoshan Township, TW;

Lee-Chung Lu, Taipei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10W 70/65 (2026.01); H10D 84/01 (2026.01); H10W 70/05 (2026.01); H10W 70/60 (2026.01); H10W 72/00 (2026.01); H10W 74/00 (2026.01); H10W 80/00 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 70/65 (2026.01); H10D 84/01 (2025.01); H10W 70/093 (2026.01); H10W 70/611 (2026.01); H10W 90/00 (2026.01); H10W 90/401 (2026.01); H10W 90/701 (2026.01); H10W 72/0198 (2026.01); H10W 74/00 (2026.01); H10W 80/312 (2026.01); H10W 80/327 (2026.01); H10W 80/334 (2026.01); H10W 90/794 (2026.01);
Abstract

Integrated circuit packages and methods of forming the same are provided. In an embodiment, a device includes: a power distribution interposer including: a first bonding layer; a first die connector in the first bonding layer; and a back-side interconnect structure including a power rail connected to the first die connector; and an integrated circuit die including: a second bonding layer directly bonded to the first bonding layer by dielectric-to-dielectric bonds; a second die connector in the second bonding layer, the second die connector directly bonded to the first die connector by metal-to-metal bonds; and a device layer on the second bonding layer, the device layer including a contact and a transistor, the transistor including a first source/drain region, the contact connecting a back-side of the first source/drain region to the second die connector.


Find Patent Forward Citations

Chen, Ming-Fa. (2026). Integrated circuit packages and methods of forming the same (U.S. Patent No. 12721194). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12721194

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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