Memory circuitry and method used in forming memory circuitry

Abstract

Memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. The stair-step region comprises a cavity comprising a flight of stairs. A lining has a specific resistance of at least 1×10ohm·m at 20° C. atop treads of the stairs of the flight of stairs. Individual of the treads comprise conducting material of one of the conductive tiers. The lining comprises at least one of (a), (b), (c), and (d), where: (a): M1M2Ohaving a specific resistance of at least 1×10ohm·m at 20° C. and where M1 and M2 are each a different one of Hf, Zr, Al, Ta, Sc, and Y; 'z' is greater than zero; and at least one of “x” and “y” is greater than zero; (b) BCOhaving a specific resistance of at least 1×10ohm·m at 20° C. and where each of “t” and “v” is greater than zero (c): BChaving a specific resistance of at least 1×10ohm·m at 20° C. and where each of “r” and “s” is greater than zero; and (d): BCNhaving a specific resistance of at least 1×10ohm·m at 20° C. and where each of “k” and “p” is greater than zero. Insulative material in the cavity is directly above the lining that comprises the at least one of the (a), the (b), the (c), and the (d). Conductive vias extend through the insulative material and the lining that comprises the at least one of the (a), the (b), the (c), and the (d). Individual of the conductive vias are directly above and directly against the conducting material of one of the individual treads. Methods are disclosed.