logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12721128 B1

PDFFull Text
Date of Patent:
Aug. 25, 2026

Filed:

Dec. 10, 2021

Standard cell layout architectures and drawing styles for 5nm and beyond

Applicant:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Inventor:

Richard T. Schultz, Fort Collins, CO (US);

Assignee:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Attorneys:

Kowert, Hood, Munyon, Rankin & Goetzel, P.C.

Rory D. Rankin

Primary Examiner:

John A Bodnar

Int. Cl.
CPC ...
H01L 29/786 (2006.01); G06F 30/39 (2020.01); G06F 30/392 (2020.01); H01L 21/768 (2006.01); H01L 27/02 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/45 (2006.01); H01L 29/49 (2006.01); H10D 30/67 (2025.01); H10D 64/66 (2025.01); H10D 89/10 (2025.01); H10W 20/00 (2026.01); H10W 20/20 (2026.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10W 20/20 (2026.01); G06F 30/39 (2020.01); G06F 30/392 (2020.01); H10D 30/6729 (2025.01); H10D 30/6735 (2025.01); H10D 30/6737 (2025.01); H10D 30/6743 (2025.01); H10D 30/6757 (2025.01); H10D 64/667 (2025.01); H10D 89/10 (2025.01); H10W 20/0698 (2026.01); H10D 84/0149 (2025.01); H10D 84/0167 (2025.01); H10D 84/0186 (2025.01); H10D 84/038 (2025.01);
Abstract

A system and method for efficiently creating layout for a standard cell are described. A standard cell to be used for an integrated circuit uses a full trench silicide strap as drain regions for a pmos transistor and an nmos transistor. Multiple unidirectional routes in metal zero are placed across the standard cell where each route connects to a trench silicide contact. Power and ground connections utilize pins rather than end-to-end rails in the standard cell. Additionally, intermediate nodes are routed in the standard cell with unidirectional routes.

Find Patent Forward Citations

Schultz, Richard. (2026). Standard cell layout architectures and drawing styles for 5nm and beyond (U.S. Patent No. 12721128). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12721128

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…