The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2026

Filed:

Dec. 16, 2022
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Shogo Mochizuki, Mechanicville, NY (US);

Gen Tsutsui, Glenmont, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 84/85 (2025.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2026.01); H10D 84/03 (2025.01); H10D 88/00 (2026.01); H10P 14/20 (2026.01); H10W 20/20 (2026.01);
U.S. Cl.
CPC ...
H10D 84/856 (2025.01); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 62/121 (2025.01); H10D 62/122 (2025.01); H10D 64/017 (2025.01); H10D 84/0167 (2025.01); H10D 84/0186 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01); H10D 88/01 (2025.01); H10P 14/3411 (2026.01); H10P 14/3462 (2026.01); H10W 20/20 (2026.01);
Abstract

A semiconductor device is provided. The semiconductor device includes a stacked field effect transistor (FET) structure. The stacked FET structure includes a bottom FET device and a top FET device. The bottom FET device has a vertically stacked gate-all-around (GAA) nanosheet (NS) structure and a first channel orientation. The top FET device is isolated from the bottom device and has a horizontally stacked structure and a second channel orientation differing from the first channel orientation.


Find Patent Forward Citations

Loading…