The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2026

Filed:

Sep. 15, 2023
Applicant:

Vanguard International Semiconductor Corporation, Hsinchu, TW;

Inventors:

Ting-Yu Chang, Zhubei City, TW;

Yeh-Ning Jou, Hsinchu City, TW;

Jian-Hsing Lee, Hsinchu City, TW;

Chieh-Yao Chuang, Kaohsiung City, TW;

Hsien-Feng Liao, Taichung City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 62/10 (2025.01); H10D 30/60 (2025.01); H10D 62/13 (2025.01); H10D 89/60 (2025.01); H10D 62/17 (2025.01);
U.S. Cl.
CPC ...
H10D 62/151 (2025.01); H10D 30/60 (2025.01); H10D 62/106 (2025.01); H10D 62/116 (2025.01); H10D 89/811 (2025.01); H10D 62/307 (2025.01);
Abstract

An electrostatic discharge (ESD) protection device is provided. A deep-well region is formed on a substrate. A first well region, a second well region, a third well region, and a fourth well region are formed on the deep-well region. A fifth well region is formed in the fourth well region. A first doped region is formed in the first well region. A second doped region is formed in the second well region. A third doped region is formed in the fourth well region. A gate structure covers the third well region. Each of the substrate, the second well region, the fourth well region, the second doped region, and the third doped region has a first conductivity type. Each of the deep-well region, the first well region, the third well region, the fifth well region, and the first doped region has a second conductivity type.


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