The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2026

Filed:

Feb. 12, 2024
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Shi Ning Ju, Hsinchu City, TW;

Kuo-Cheng Chiang, Hsinchu County, TW;

Chih-Hao Wang, Hsinchu County, TW;

Kuan-Lun Cheng, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 62/00 (2026.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 64/01 (2025.01); H10D 64/23 (2025.01); H10D 84/01 (2026.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01); H10D 84/85 (2025.01); H10W 10/17 (2026.01); H10W 20/00 (2026.01); H10W 20/41 (2026.01); H10W 20/42 (2026.01); H10W 10/00 (2026.01);
U.S. Cl.
CPC ...
H10D 30/6211 (2025.01); H10D 30/024 (2025.01); H10D 30/0243 (2025.01); H10D 30/6219 (2025.01); H10D 62/021 (2025.01); H10D 64/017 (2025.01); H10D 64/254 (2025.01); H10D 84/0147 (2025.01); H10D 84/0149 (2025.01); H10D 84/0158 (2025.01); H10D 84/0186 (2025.01); H10D 84/0188 (2025.01); H10D 84/038 (2025.01); H10D 84/834 (2025.01); H10D 84/853 (2025.01); H10W 20/069 (2026.01); H10W 20/42 (2026.01); H10W 20/427 (2026.01); H10W 20/435 (2026.01); H10D 84/013 (2025.01); H10W 10/014 (2026.01); H10W 10/17 (2026.01);
Abstract

A semiconductor structure includes a power rail on a back side of the semiconductor structure, a first interconnect structure on a front side of the semiconductor structure, and a source feature, a drain feature, a first semiconductor fin, and a gate structure that are between the power rail and the first interconnect structure. The first semiconductor fin connects the source feature and the drain feature. The gate structure is disposed on a front surface and two side surfaces of the first semiconductor fin. The semiconductor structure further includes an isolation structure disposed between the power rail and the drain feature and between the power rail and the first semiconductor fin and a via penetrating through the isolation structure and connecting the source feature to the power rail.


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