The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2026

Filed:

Jan. 12, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Myunghun Woo, Hwaseong-si, KR;

Jooheon Kang, Seoul, KR;

Hyunmog Park, Seoul, KR;

Jongho Woo, Hwaseong-si, KR;

Suseong Noh, Suwon-si, KR;

Youngji Noh, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/27 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/49 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/49 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02);
Abstract

A semiconductor device includes a gate stack structure including alternately stacked insulating patterns and conductive patterns; a memory channel structure extending through the gate stack structure; and a bit line pad on the memory channel structure, wherein the memory channel structure includes a variable resistance layer, a channel layer surrounding the variable resistance layer, and a channel insulating layer surrounding the channel layer, and a bottom surface of the bit line pad contacts a top surface of the variable resistance layer, a top surface of the channel layer, and a top surface of the channel insulating layer.


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