The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2026

Filed:

Jul. 14, 2023
Applicant:

Invention and Collaboration Laboratory Pte. Ltd., Singapore, SG;

Inventors:

Chao-Chun Lu, Taipei City, TW;

Chun Shiah, Hsinchu City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01); G11C 11/406 (2006.01); G11C 11/4076 (2006.01); G11C 11/4091 (2006.01);
U.S. Cl.
CPC ...
H10B 12/488 (2023.02); G11C 11/40615 (2013.01); G11C 11/4076 (2013.01); G11C 11/4091 (2013.01); H10B 12/315 (2023.02); H10B 12/482 (2023.02); H10B 12/50 (2023.02); H10B 12/05 (2023.02);
Abstract

A semiconductor memory structure includes a semiconductor substrate, a plurality of DRAM (dynamic random access memory) cells, a bit line, a sense amplifier, and a local word line. The semiconductor substrate has a top surface. Each DRAM cell includes an access transistor and a storage capacitor. The bit line has a first terminal extended along the plurality of DRAM cells to a second terminal, and the bit line is coupled to each access transistor of the plurality of DRAM cells. The sense amplifier is coupled to the first terminal of the bit line. The local word line is connected to a gate conductive region of an access transistor of a first DRAM cell in the plurality of DRAM cells. A rising time or a falling time of a voltage signal in the local word line is less than 4 ns.


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