The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2026

Filed:

Jun. 24, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chieh Jen Huang, Hsinchu, TW;

Mu-Shan Lin, Hsinchu, TW;

Wen-Hung Huang, Hsinchu, TW;

Shu-Chun Yang, Hsinchu, TW;

Wei Chih Chen, Hsinchu, TW;

Chien-Chun Tsai, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/003 (2006.01); H03K 5/24 (2006.01); H03K 19/0185 (2006.01);
U.S. Cl.
CPC ...
H03K 19/00384 (2013.01); H03K 5/2472 (2013.01); H03K 19/018521 (2013.01);
Abstract

A system (for determining a lineup amongst a roster of all PFETs and all NFETs that are slaves in a subject group of pull-up-pull-down-inverters (PUDIs) that are coupled in parallel) includes: a comparator to make a comparison between a reference voltage and an output of the subject group. The controller performs: an assessment of a candidate lineup chosen from the roster including setting states of PFET-selection selection signals and NFET-selection signals according to the candidate lineup, and a manipulation based on the comparison including setting the starting-lineup to be the candidate lineup or modifying the candidate lineup and repeating the assessment and manipulation.


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