The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2026

Filed:

Jun. 12, 2024
Applicant:

Sandisk Technologies, Inc., Milpitas, CA (US);

Inventors:

Jiacen Guo, Cupertino, CA (US);

Xiang Yang, Santa Clara, CA (US);

Assignee:

Sandisk Technologies, Inc., Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/06 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3459 (2013.01);
Abstract

An apparatus includes a plurality of memory cells connected to word lines and bit lines and configured to retain a threshold voltage corresponding to one of a plurality of data states following a program operation; and a control circuit connected to the word lines and the bit lines. The control circuit is configured to use, during a setup clock of a loop of a plurality of loops of a program-verify operation, a first verify voltage ramping time period of a plurality of verify voltage ramping time periods based on a data state being verified during the loop, and use, during a setup clock of another loop of a plurality of loops of a program-verify operation, a second verify voltage ramping time period of the plurality of verify voltage ramping time periods based on a data state being verified during the other loop.


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