The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2026

Filed:

Aug. 08, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;

Inventor:

Gerben Doornbos, Kessel-Lo, BE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 15/04 (2006.01); G11C 5/06 (2006.01); H10B 41/10 (2023.01); H10B 41/30 (2023.01); H10B 51/10 (2023.01); H10B 51/30 (2023.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 30/68 (2025.01); H10D 30/69 (2025.01); H10W 20/41 (2026.01); H10W 20/42 (2026.01);
U.S. Cl.
CPC ...
G11C 15/046 (2013.01); G11C 5/063 (2013.01); H10B 41/10 (2023.02); H10B 41/30 (2023.02); H10B 51/10 (2023.02); H10B 51/30 (2023.02); H10D 30/0411 (2025.01); H10D 30/0415 (2025.01); H10D 30/6757 (2025.01); H10D 30/68 (2025.01); H10D 30/6891 (2025.01); H10D 30/701 (2025.01); H10W 20/42 (2026.01); H10W 20/435 (2026.01);
Abstract

A four transistor ternary content-addressable memory cell includes a first series connection of a first non-hysteretic transistor (e.g., a thin-film transistor) and a first memory transistor (e.g., a thin-film transistor) including a first memory element configured to store a first binary bit; and a second series connection of a second non-hysteretic transistor and a second memory transistor including a second memory element configured to store a second binary bit. The first series connection and the second series connection are connected in parallel between a match line and a word line.


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