Memory cell arrangement and method of reading a capacitive memory cell

Abstract

Various aspects relate to a memory cell arrangement including: bitlines; wordlines; platelines; capacitive memory cells, wherein each of the capacitive memory cells is connected to and selectively addressable by a corresponding bitline, a corresponding wordline, and a corresponding plateline; a control circuit configured to carry out a read-out operation to read a memory state of a capacitive memory cell, the read-out operation including: charging the corresponding bitline to a first characteristic voltage by applying a plateline voltage having a first plateline voltage value at the corresponding plateline and by applying a wordline voltage at the corresponding wordline; decreasing the plateline voltage from the first plateline voltage value to a second plateline voltage value to thereby discharge the corresponding bitline from the first characteristic voltage to a second characteristic voltage; and determining the memory state of the capacitive memory cell based on sensing the second characteristic voltage.