The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2026

Filed:

Dec. 03, 2024
Applicant:

Stmicroelectronics International N.v., Geneva, CH;

Inventors:

Om Ranjan, Greater Noida, IN;

Vivek Kumar Sood, Lucknow, IN;

Sankara Mallikarjuna Rao, Greater Noida, IN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); H03M 13/11 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0284 (2013.01); H03M 13/1157 (2013.01); G06F 2212/1052 (2013.01);
Abstract

According to an embodiment, a method for operating a memory system includes receiving data bits at a memory controller for storage in memory, remapping the data bits according to a predetermined scheme as they are transmitted from the controller to memory via a bus, storing the remapped bits in memory, reading the remapped bits from memory via the bus, and inverse remapping the bits to restore their original order as they are transmitted back to the controller. The remapping enhances fault tolerance by spatially separating related bits. The scheme may use techniques like multiplexing, cyclic shifting, or pseudo-random distribution. The remapping can be implemented through hardwired bus connections without adding clock cycles. The method improves resilience to multi-bit errors in wide-word volatile memories used in safety-critical applications, while maintaining compatibility with existing error detection methods.


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