The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2026

Filed:

Aug. 15, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Marc Beuchat, Orangevale, CA (US);

Eric Samson, Folsom, CA (US);

Philip Meyer, Draper, UT (US);

Namita Sharma, New Delhi, IN;

Pallavi T J, Bangalore Rural, IN;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/08 (2006.01); G06F 1/20 (2006.01); G06F 1/3234 (2019.01); G06F 1/324 (2019.01); G06F 1/3296 (2019.01); G06T 1/20 (2006.01); G06T 1/60 (2006.01);
U.S. Cl.
CPC ...
G06F 1/08 (2013.01); G06T 1/20 (2013.01); G06T 1/60 (2013.01);
Abstract

A system that includes first circuitries to operate at a first clock frequency, second circuitries to operate at a second clock frequency, and circuitry to adjust the first and second clock frequencies. In some examples, the circuitry is to selectively adjust the first and second clock frequencies provided to the respective first circuitries and the second circuitries according to a target ratio based on temperature and power consumption of the first circuitries and the second circuitries, wherein the target ratio is based on clock frequencies of the first circuitries and the second circuitries, stall time of the first circuitries, and dynamic capacitance of the first circuitries and the second circuitries.


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