The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2026

Filed:

Mar. 31, 2023
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Gamal Refai-Ahmed, Santa Clara, CA (US);

Chuan Xie, Fremont, CA (US);

Chi-Yi Chao, New Taipei City, TW;

Suresh Ramalingam, Fremont, CA (US);

Nagadeven Karunakaran, Butterworth, MY;

Ferdinand F. Fernandez, San Jose, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02B 6/38 (2006.01); G02B 6/42 (2006.01);
U.S. Cl.
CPC ...
G02B 6/3849 (2013.01); G02B 6/381 (2013.01); G02B 6/4295 (2013.01);
Abstract

A method of fabricating a chip package is provided, and a chip package fabricated using the same are provided. The method includes connecting a photonic die to a substrate of the chip package and attaching a protection apparatus to the substrate. The method also includes attaching a photonic connector to the photonic die. At least a portion of the photonic connector is disposed inside a housing of the protection apparatus. A fabrication process is performed on the chip package while the photonic connector is inside the housing. After processing, the photonic connector is removed from the housing.


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