The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2026

Filed:

Aug. 11, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Hsien-Wei Chen, Hsinchu, TW;

Sung-Feng Yeh, Taipei City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/78 (2006.01); H10P 72/70 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 74/01 (2026.01); H10W 74/10 (2026.01); H10W 74/43 (2026.01); H10W 74/47 (2026.01); H10W 90/00 (2026.01); H10W 80/00 (2026.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); H10P 72/74 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 74/016 (2026.01); H10W 74/111 (2026.01); H10W 74/43 (2026.01); H10W 74/47 (2026.01); H10W 80/312 (2026.01); H10W 80/327 (2026.01); H10W 90/794 (2026.01);
Abstract

A semiconductor package with two interposers, and the method of forming the same are provided. The semiconductor package may include a first interposer, a first semiconductor die on the first interposer, a second interposer on the first semiconductor die, and a second semiconductor die on the second interposer. The second interposer may be between the first semiconductor die and the second semiconductor die. The first semiconductor die may be bonded to the first interposer by metal-to-metal bonding and dielectric-to-dielectric bonding. The second semiconductor die may be bonded to the second interposer by metal-to-metal bonding and dielectric-to-dielectric bonding.


Find Patent Forward Citations

Chen, Hsien-Wei. (2026). Semiconductor package and method (U.S. Patent No. 12708049). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12708049

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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