The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2026

Filed:

Jun. 11, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventor:

Chung-Hui Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10W 70/60 (2026.01); H10W 70/63 (2026.01); H10W 70/65 (2026.01); H10W 72/00 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 70/611 (2026.01); H10W 70/635 (2026.01); H10W 70/65 (2026.01); H10W 72/00 (2026.01); H10W 90/401 (2026.01);
Abstract

An integrated circuit (IC) device includes a substrate, active regions including a first active region, gate regions over the active regions, first and second conductive patterns, and a first through via structure. The active regions are over a first side of the substrate. The first conductive pattern is over and electrically coupled to the first active region. The first through via structure extends from a second side, through the substrate, to the first side in electrical contact with the first active region. The second conductive pattern is under the second side of the substrate and electrically coupled to the first through via structure. The gate regions and active regions together configure transistors, including a pair of adjacent transistors on opposite sides of the first active region. Each transistor in the pair of adjacent transistors is electrically coupled to be in an always-OFF state, or has the corresponding gate region floating.


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