Wafer level multi-die structure formation

Abstract

An array of dies is formed over a substrate. Each of the dies contains a plurality of functional transistors. A plurality of first seal rings each surround a respective one of the dies in a top view. The first seal rings define a plurality of corner regions that are disposed outside of the first seal rings and between corners of respective subsets of the dies. A plurality of structures is disposed within the corner regions. The structures include test structures, dummy structures, process monitor patterns, alignment marks, or overlay marks. Electrical interconnection elements are disposed between each pair of adjacent dies in the array of dies in the top view. The electrical interconnection elements electrically interconnect the dies in the array with one another. A second seal ring surrounds the array of dies, the first seal rings, and the structures in the top view.