The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2026

Filed:

Jan. 31, 2024
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Edward P. Hammond, Hillsborough, CA (US);

Tsutomu Tanaka, Santa Clara, CA (US);

Alexander V. Garachtchenko, Brentwood, CA (US);

Dmitry A Dzilno, Sunnyvale, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10P 72/72 (2026.01); H01L 21/683 (2006.01); H10P 72/00 (2026.01);
U.S. Cl.
CPC ...
H10P 72/722 (2026.01); H10P 72/0604 (2026.01);
Abstract

A pedestal may be configured to support a substrate during a semiconductor process. An electrostatic chuck (ESC) may include electrodes embedded in the pedestal that are configured to deliver a chucking voltage to the pedestal during the semiconductor process. A power source coupled to an electrode may be configured to provide a signal having a frequency range to the electrode during the semiconductor process. A controller may be configured to receive a measurement of an impedance when the frequency range is applied to the electrode. The impedance measurements my then be used to determine a chucking state of the substrate, such as whether an airgap is present between the substrate and the pedestal during the semiconductor process.


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