The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2026

Filed:

Mar. 03, 2021
Applicant:

Sony Semiconductor Solutions Corporation, Kanagawa, JP;

Inventors:

Hitoshi Okano, Kanagawa, JP;

Kan Shimizu, Kanagawa, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10F 39/00 (2025.01); H10F 39/18 (2025.01); H10W 72/20 (2026.01); H10W 72/90 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10F 39/805 (2025.01); H10F 39/18 (2025.01); H10F 39/809 (2025.01); H10W 72/20 (2026.01); H10W 72/90 (2026.01); H10W 72/952 (2026.01); H10W 90/724 (2026.01); H10W 90/792 (2026.01);
Abstract

The present technology relates to an imaging element and a semiconductor chip that can implement a low height of the imaging element. A first chip including a photo diode; and a second chip including a circuit processing a signal transmitted from the photo diode are stacked, and a charging film is disposed on a second face of the second chip that is on a side opposite to a first face on which the first chip is stacked. The charging film is disposed in a part or the entirety of the second face. For example, the present technology can be applied to an imaging element, in which a plurality of chips are configured to be stacked, that can implement a low height and a small size.


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