The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2026

Filed:

Oct. 18, 2023
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Andrew W. Yeoh, Portland, OR (US);

Joseph Steigerwald, Forest Grove, OR (US);

Jinhong Shin, Portland, OR (US);

Vinay Chikarmane, Portland, OR (US);

Christopher P. Auth, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/033 (2006.01); H01L 21/28 (2006.01); H01L 21/285 (2006.01); H01L 21/308 (2006.01); H01L 21/311 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 27/02 (2006.01); H01L 27/088 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H10B 10/00 (2023.01); H10D 1/47 (2025.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 30/69 (2025.01); H10D 62/00 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 62/822 (2025.01); H10D 62/834 (2025.01); H10D 64/01 (2025.01); H10D 64/23 (2025.01); H10D 64/68 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01); H10D 84/85 (2025.01); H10D 89/10 (2025.01); H10P 14/20 (2026.01); H10P 14/40 (2026.01); H10P 50/00 (2026.01); H10P 50/28 (2026.01); H10P 76/40 (2026.01); H10W 10/00 (2026.01); H10W 10/17 (2026.01); H10W 20/00 (2026.01); H10W 20/41 (2026.01); H10W 20/42 (2026.01); H10W 20/43 (2026.01); H10W 20/44 (2026.01); H10W 20/48 (2026.01); H10P 14/692 (2026.01); H10P 14/694 (2026.01); H10W 74/15 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10D 64/017 (2025.01); H10B 10/12 (2023.02); H10D 1/47 (2025.01); H10D 1/474 (2025.01); H10D 30/024 (2025.01); H10D 30/0245 (2025.01); H10D 30/62 (2025.01); H10D 30/6211 (2025.01); H10D 30/6213 (2025.01); H10D 30/6219 (2025.01); H10D 30/792 (2025.01); H10D 30/794 (2025.01); H10D 30/795 (2025.01); H10D 30/797 (2025.01); H10D 62/021 (2025.01); H10D 62/115 (2025.01); H10D 62/116 (2025.01); H10D 62/151 (2025.01); H10D 62/822 (2025.01); H10D 62/834 (2025.01); H10D 64/0112 (2026.01); H10D 64/01354 (2026.01); H10D 64/015 (2025.01); H10D 64/021 (2025.01); H10D 64/259 (2025.01); H10D 64/689 (2025.01); H10D 84/0151 (2025.01); H10D 84/0158 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/0172 (2025.01); H10D 84/0177 (2025.01); H10D 84/0181 (2025.01); H10D 84/0186 (2025.01); H10D 84/0188 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/834 (2025.01); H10D 84/853 (2025.01); H10D 84/856 (2025.01); H10D 89/10 (2025.01); H10P 14/27 (2026.01); H10P 14/3411 (2026.01); H10P 14/418 (2026.01); H10P 50/282 (2026.01); H10P 50/695 (2026.01); H10P 50/73 (2026.01); H10P 76/4085 (2026.01); H10W 10/014 (2026.01); H10W 10/0145 (2026.01); H10W 10/17 (2026.01); H10W 20/035 (2026.01); H10W 20/037 (2026.01); H10W 20/056 (2026.01); H10W 20/069 (2026.01); H10W 20/071 (2026.01); H10W 20/077 (2026.01); H10W 20/081 (2026.01); H10W 20/089 (2026.01); H10W 20/42 (2026.01); H10W 20/425 (2026.01); H10W 20/43 (2026.01); H10W 20/435 (2026.01); H10W 20/4403 (2026.01); H10W 20/48 (2026.01); H10D 30/0212 (2025.01); H10D 30/6212 (2025.01); H10D 30/791 (2025.01); H10D 84/0135 (2025.01); H10D 84/0149 (2025.01); H10P 14/69215 (2026.01); H10P 14/69433 (2026.01); H10P 76/405 (2026.01); H10W 20/063 (2026.01); H10W 74/15 (2026.01); H10W 90/724 (2026.01); H10W 90/734 (2026.01);
Abstract

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.


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