Vertical mosfet device

Abstract

The present disclosure relates to a vertical MOSFET device, a manufacturing method and application thereof. The method includes: forming a first silicon layer, a first germanium-silicon layer, a second germanium-silicon layer, a third germanium-silicon layer and a second silicon layer that are vertically stacked from bottom to top on a substrate, where molar contents of germanium in the first germanium-silicon layer and the third germanium-silicon layer are both greater than the content of germanium in the second germanium-silicon layer; etching to form a nano stack structure; selectively etching the first germanium-silicon layer and the third germanium-silicon layer to form a first groove and a third groove; forming inner spacers of an extension region in the first groove and the third groove; selectively etching the second germanium-silicon layer to form a gate groove; forming a dummy gate in the gate groove; forming sources/drains; forming an active region with a shallow trench isolation layer; and removing the dummy gate to form a gate dielectric layer and a gate. The present disclosure can well control the size of channel, the size of inner spacers of the extension region, the size of the gates, and the like, and is applicable to either nanosheet or nanowire structures.