The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2026

Filed:

Aug. 31, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

MD Zahid Hossain, Boise, ID (US);

Martin Popp, Meridian, ID (US);

Xiaosong Zhang, Boise, ID (US);

Surendranath C. Eruvuru, Boise, ID (US);

Suvra Sarkar, Singapore, SG;

Tianqi Xu, JiaDing, CN;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 43/40 (2023.01); H10B 41/40 (2023.01); H10B 41/50 (2023.01);
U.S. Cl.
CPC ...
H10B 43/40 (2023.02); H10B 41/40 (2023.02); H10B 41/50 (2023.02);
Abstract

A variety of applications can include apparatus having a memory device structured with a circuit under array (CuA) architecture. A page buffer region in the CuA can be formed with a periphery region that is horizontally adjacent to the page buffer region. Contacts to gates for transistors in the page buffer region can be formed to land only on these gates, separating and electrically isolating the contacts and associated gates from each other in the page buffer region. Contacts to gates for transistors in the periphery region can be formed to land on conductive regions disposed on gates for transistors in the periphery region.


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