The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2026

Filed:

Jun. 27, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventor:

Wei Shuo Lin, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 5/12 (2006.01); H03K 5/00 (2006.01); H03L 7/081 (2006.01); H04L 7/00 (2006.01); H04L 7/033 (2006.01); H04L 23/02 (2006.01);
U.S. Cl.
CPC ...
H04L 7/0025 (2013.01); H03K 5/00 (2013.01); H03L 7/0814 (2013.01); H04L 7/0337 (2013.01); H03K 2005/00052 (2013.01);
Abstract

A device includes a transmission clock circuit that includes a phase interpolator circuit and a transmission differential to quadrature phase generator. The phase interpolator circuit interpolates phases and provides phase interpolated first clock signals and phase interpolated second clock signals. The transmission differential to quadrature phase generator, duty cycle corrects each of the phase interpolated first clock signals and the phase interpolated second clock signals, quadrature error corrects each of the duty cycle corrected phase interpolated first clock signals and the duty cycle corrected phase interpolated second clock signals, outputs transmission clock signals based on the quadrature error corrected duty cycle corrected phase interpolated first clock signals, and outputs multiple clock phases and a track signal based on the quadrature error corrected duty cycle corrected phase interpolated second clock signals.


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