Program verify pairing in a multi-level cell memory device

Abstract

Control logic in a memory device initiates a loop of a program operation comprising (a) a program phase where a plurality of memory cells associated with a selected wordline in a block of the memory array are programmed to respective programming levels and (b) a corresponding program verify phase. The control logic further identifies memory cells associated with a first sub-set of programming levels to be verified during the program verify phase, the first sub-set comprising two or more dynamically selected programming levels comprising at least a lowest programming level and a second lowest programing level. The control logic further performs concurrent sensing operations on the identified memory cells during the program verify phase to determine whether the identified memory cells were programmed to respective program verify threshold voltages corresponding to the first sub-set of the plurality of programming levels during the program phase.