Data routing for error correction in stacked memory architectures

Abstract

Methods, systems, and devices for data routing for error correction in stacked memory architectures are described. A system supports error correction of bits of data communicated between a first semiconductor die (e.g., an array die) and a second semiconductor die (e.g., a logic die). For example, an interface of the second semiconductor die receives data stored at a memory array of the first semiconductor die. The interface includes error correction engines each operable to correct one or more bit errors. The interface also includes logic circuitry operable to route physically-grouped subsets of the received data to respective error correction engines, and such subsets are configured to allocate the error correction engines in manner that improves a likelihood that physically-grouped errors in the system can be corrected. The interface outputs the data to a host system after the error control operations are performed.