Circuitry and methods for implementing capabilities using narrow registers

Abstract

Systems, methods, and apparatuses for implementing capabilities using narrow registers are described. In certain examples, a hardware processor core comprises a capability management circuit to check a capability for a memory access request, the capability comprising an address field, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of an address space to which the capability authorizes access; a decoder circuit to decode a single instruction into a decoded single instruction, the single instruction comprising fields to indicate a memory address that stores the capability and a single destination register, and an opcode to indicate that an execution circuit is to load a first proper subset of the capability from the memory address into the single destination register and load a second proper subset of the capability from the memory address into an implicit second destination register; and the execution circuit to execute the decoded single instruction according to the opcode.