Circuitry and methods for implementing capability-based compartment switches with descriptors

Abstract

Systems, methods, and apparatuses for implementing capability-based compartment switches with descriptors are described. In certain examples, a hardware processor core comprises a capability management circuit to check a capability for a memory access request, the capability comprising an address field and a bounds field that is to indicate a lower bound and an upper bound of an address range to which the capability authorizes access; a decoder circuit to decode a single instruction into a decoded single instruction, the single instruction comprising one or more fields to indicate a first compartment descriptor that identifies a first capability to a first state element in a first compartment of memory and a second capability to a second state element in the first compartment of the memory, and an opcode to indicate that an execution circuit is to load the first capability from the first compartment descriptor of the memory into a first register to enable the capability management circuit to determine whether a first bounds field of the first capability authorizes an access to the first state element in the first compartment of the memory, and load the second capability from the first compartment descriptor of the memory into a second register to enable the capability management circuit to determine that a second bounds field of the second capability authorizes an access to the second state element in the first compartment of the memory; and the execution circuit to execute the decoded single instruction according to the opcode.