Flash translation layer write path architecture for increased throughput

Abstract

A processing device includes flash translation layer logic to be coupled to a memory device and that includes cursor logic to generate a criteria set associated with generating a backend command to be sent the memory device and streamer logic to access and employ the criteria set, e.g., aggregates translation units (TUs) received in one or more write messages. The criteria set enables accessing the plurality of TUs within a first format, of the one or more write messages, that depends on a data path associated with the one or more write messages. The streamer logic formats the aggregated TUs into the backend command having a second format for transmittal to the memory device. The backend command is to direct the memory device in writing TU data, associated with the TUs, to a memory array of the memory device.