The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2026

Filed:

Jun. 11, 2021
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Alexander Frey, Lappersdorf, DE;

Bernhard Goller, Villach, AT;

Iris Moder, Villach, AT;

Ingo Muri, Villach, AT;

Alfred Sigl, Sinzing, DE;

Tobias Weindler, Teublitz, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10F 39/00 (2025.01); G01S 17/894 (2020.01); H10D 30/66 (2025.01); H10F 39/12 (2025.01); H10F 39/18 (2025.01); H10P 52/00 (2026.01); H10W 46/00 (2026.01);
U.S. Cl.
CPC ...
H10F 39/026 (2025.01); G01S 17/894 (2020.01); H10D 30/66 (2025.01); H10F 39/024 (2025.01); H10F 39/18 (2025.01); H10F 39/199 (2025.01); H10F 39/8057 (2025.01); H10F 39/8063 (2025.01); H10P 52/00 (2026.01); H10W 46/00 (2026.01); H10W 46/301 (2026.01);
Abstract

A method of manufacturing a semiconductor device is described. The method includes providing a semiconductor substrate. The semiconductor substrate includes a high-doped semiconductor substrate layer, a high-doped semiconductor device layer, and a low-doped semiconductor etch stop layer arranged between the high-doped semiconductor substrate layer and the high-doped semiconductor device layer. The high-doped semiconductor substrate layer is removed, wherein the removing includes dopant selective chemical etching stopping at the low-doped semiconductor etch stop layer. Further, the low-doped semiconductor etch stop layer is thinned to generate an exposed surface of the high-doped semiconductor device layer.


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