Semiconductor device having nanosheet transistor and methods of fabrication thereof

Abstract

Various embodiments of the present disclosure provide a semiconductor device structure. In one embodiment, the semiconductor device structure includes a plurality of semiconductor layers vertically stacked over a substrate, a source/drain feature in contact with each of the plurality of the semiconductor layers, an inner spacer disposed between two adjacent semiconductor layers, a gate electrode layer surrounding a portion of each of the plurality of the semiconductor layers, a gate dielectric layer disposed between the semiconductor layer and the gate electrode layer, a gate spacer in contact with a portion of the gate dielectric layer. The semiconductor device structure further includes a first cap layer comprising a first portion disposed between and in contact with the source/drain feature and the gate spacer, and a second portion disposed between and in contact with gate spacer and the inner spacer.