The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2026

Filed:

Jul. 19, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventor:

Mitsunari Sukekawa, Hiroshima, JP;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01);
U.S. Cl.
CPC ...
H10B 12/485 (2023.02); H10B 12/315 (2023.02); H10B 12/34 (2023.02);
Abstract

An apparatus comprises semiconductive pillar structures each individually comprising a digit line contact region disposed laterally between two storage node contact regions. At least one semiconductive pillar structure of the semiconductive pillar structures comprises a first end portion comprising a first storage node contact region, a second end portion comprising a second storage node contact region, a central portion between the first end portion and the second end portion and comprising the digit line contact region, a first intervening portion between the first end portion and the central portion, and a second intervening portion between the second end portion and the central portion. A longitudinal axis of each of the first intervening portion and the second intervening portion is oriented at an angle with respect to a longitudinal axis of the central portion. Related memory devices, electronic systems, and methods of forming the apparatus are also described.


Find Patent Forward Citations

Sukekawa, Mitsunari. (2026). Apparatuses including semiconductive pillar structures, and related methods, memory devices, and electronic systems (U.S. Patent No. 12701694). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12701694

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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