The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2026

Filed:

Aug. 08, 2024
Applicant:

Synopsys, Inc., Sunnyvale, CA (US);

Inventors:

Ankit Agrawal, Greater Noida, IN;

Shailesh Kumar, Nodia, IN;

Assignee:

Synopsys, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/082 (2006.01); H03K 17/10 (2006.01); H03K 19/0185 (2006.01);
U.S. Cl.
CPC ...
H03K 17/0822 (2013.01); H03K 17/102 (2013.01); H03K 19/018521 (2013.01);
Abstract

A voltage driver for supplying a supply voltage includes multiple PMOS transistors, multiple NMOS transistors, a pad, impedance divider circuits, NMOS clampers, PMOS clampers, a gate protection circuit, and a bulk protection circuit. A maximum of the supply voltage is N times a maximum of the drain-source voltage of each transistor. The pad is configured to receive a voltage signal for dynamically controlling gates of a subset of the NMOS transistors and a subset of the PMOS transistors. The impedance divider circuits are configured to generate voltage signals. The NMOS clampers and PMOS clampers are configured to receive reference voltages and limited voltage signals to generate output. The gate protection circuit are between outputs of the clampers and gates of the transistors. The bulk protection circuit is between bodies of the transistors and the impedance divider circuit.


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