The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2026

Filed:

Jan. 26, 2024
Applicant:

Neo Semiconductor, Inc., San Jose, CA (US);

Inventor:

Fu-Chang Hsu, San Jose, CA (US);

Assignee:

NEO Semiconductor, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 5/06 (2006.01); H10B 41/20 (2023.01); H10B 43/20 (2023.01);
U.S. Cl.
CPC ...
G11C 16/0483 (2013.01); G11C 5/063 (2013.01); H10B 41/20 (2023.02); H10B 43/20 (2023.02);
Abstract

Various 3D cells, array structures, and processes are disclosed. In an embodiment, a 3D cell structure includes a NOR-type memory cell array having rows of memory cells, and each memory cell stores data that controls a cell current for that memory cell. The structure also includes bit lines connected to the rows of memory cells, and each bit line is connected to one memory cell in each of row. The cell structure also includes source lines connected to the rows of memory cells, respectively, and each source line is connected to all the memory cells of a corresponding row of memory cells. The structure is configured so that input signals applied to the bit lines cause cell currents to flow through the memory cells, and in each row of memory cells, selected cell currents combine to form a row cell current that flows on the associated source line.


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