The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 04, 2026
Filed:
Dec. 20, 2023
Micron Technology, Inc., Boise, ID (US);
Jacob Robert Anderson, Meridian, ID (US);
Micron Technology, Inc., Boise, ID (US);
Abstract
Methods, systems, and devices for memory array circuit arrangement are described. A memory device may include a memory subarray, which may include a complementary metal oxide semiconductor (CMOS) circuitry under array (CuA) circuitry area and a word line driver region (e.g., word line driver circuitry) or a digit line driver region (e.g., digit line driver circuitry, sense amplifier circuitry multiplexed with the digit line driver circuitry). The memory subarray may include a first interconnect extending in a first and traversing at least a first portion of the CuA circuitry area of the memory subarray. The first interconnect may be coupled with the first portion of the CuA circuitry area and a first interconnection layer. Additionally, each memory subarray may include a second interconnect extending in a second direction and traversing at least a second portion of the CuA circuitry area of the memory subarray.