In-memory computation device for implementing at least a multilayer neural network

Abstract

An in-memory computation (IMC) device is configured to receive input data and provide intermediate output data. A word line activation circuit receives input data and provides corresponding word line activation signals. A memory array includes memory cells in a matrix arrangement coupled to bit lines and to word lines. Each bit line is traversed by a respective bit line current depending on the memory cells connected to the bit line. Selectors each coupled to a respective part of the bit lines are configured to select one of the respective bit lines. A digital detector for each selector is electrically connected, through the respective selector, with the respective bit line selected. The digital detectors sample the respective bit line currents and, in response to the bit line currents, provide the respective intermediate output data.