The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 04, 2026
Filed:
Nov. 02, 2022
Applicant:
Xilinx, Inc., San Jose, CA (US);
Inventors:
Surya Rajendra Swamy Saranam Chongala, Srikakulam, IN;
Nikhil Arun Dhume, Hyderbad, IN;
Krishnan Srinivasan, San Jose, CA (US);
Dinesh D. Gaitonde, Fremont, CA (US);
Assignee:
XILINX, INC., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/3953 (2020.01);
U.S. Cl.
CPC ...
G06F 30/3953 (2020.01);
Abstract
Embodiments herein describe a network on chip (NoC) that implements multi-path routing (MPR) between an ingress logic block and an egress logic block. The multiple paths between the ingress and egress logic blocks can be assigned different alias destination IDs corresponding to the same destination ID. The NoC can use the alias destination IDs to route the packets along the different paths through interconnected switches in the NoC.