The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 28, 2026
Filed:
Aug. 30, 2021
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Inventors:
Yung-Ching Chao, Yunlin County, TW;
Wei-Han Chiang, Hsinchu, TW;
Peng-Yuan Jung, Hsinchu, TW;
Chin-Wei Kang, Tainan City, TW;
Cheng-Jen Lin, Kaohsiung City, TW;
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 74/10 (2026.01); H10W 20/20 (2026.01); H10W 42/00 (2026.01); H10W 70/60 (2026.01); H10W 70/62 (2026.01); H10W 70/63 (2026.01); H10W 70/65 (2026.01); H10W 70/67 (2026.01); H10W 70/685 (2026.01); H10W 72/00 (2026.01); H10W 72/20 (2026.01); H10W 72/29 (2026.01); H10W 72/90 (2026.01); H10W 74/01 (2026.01);
U.S. Cl.
CPC ...
H10W 74/147 (2026.01); H10W 20/20 (2026.01); H10W 20/211 (2026.01); H10W 20/222 (2026.01); H10W 20/233 (2026.01); H10W 42/00 (2026.01); H10W 70/60 (2026.01); H10W 70/611 (2026.01); H10W 70/62 (2026.01); H10W 70/635 (2026.01); H10W 70/65 (2026.01); H10W 70/67 (2026.01); H10W 70/685 (2026.01); H10W 70/686 (2026.01); H10W 70/687 (2026.01); H10W 72/01938 (2026.01); H10W 72/29 (2026.01); H10W 72/923 (2026.01); H10W 72/9415 (2026.01); H10W 74/01 (2026.01); H10W 72/01257 (2026.01); H10W 72/252 (2026.01); H10W 72/952 (2026.01);
Abstract
An integrated circuit structure includes a semiconductor substrate, a passivation layer, a first protective layer, and a second protective layer. The passivation layer is over the semiconductor substrate. The first protective layer is over the passivation layer. The second protective layer is over the first protective layer, wherein a boundary of the first protective layer is confined within the second protective layer.