The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2026

Filed:

Apr. 17, 2023
Applicant:

Ciena Corporation, Hanover, MD (US);

Inventors:

Simon Savard, Quebec, CA;

Raphael Beaupré-Laflamme, Quebec, CA;

François Pelletier, Quebec, CA;

Assignee:

Ciena Corporation, Hanover, MD (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10P 72/00 (2026.01); B25B 11/00 (2006.01); H10P 72/10 (2026.01); H10P 72/78 (2026.01);
U.S. Cl.
CPC ...
H10P 72/18 (2026.01); B25B 11/005 (2013.01); H10P 72/78 (2026.01);
Abstract

An apparatus for securing a wafer, the wafer having a first side comprising a plurality of fabricated structure regions and a second side that has at least one region that is exposed for fabrication when the wafer is secured, comprises: a carrier base configured to receive the wafer, the carrier base comprising one or more alignment features for aligning the wafer to the carrier base; and a plurality of support structures arranged on the carrier base. Three or more of the support structures are each configured to contact the first side of the wafer when the wafer is secured to the carrier base, and arranged on the carrier base to contact the first side of the wafer at a location on the first side of the wafer that is between at least two of the plurality of fabricated structure regions.


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