The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2026

Filed:

Apr. 12, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Dongjin Lee, Seoul, KR;

Junhee Lim, Seoul, KR;

Kangoh Yun, Hwaseong-si, KR;

Sohyun Lee, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/83 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10W 10/00 (2026.01); H10W 10/17 (2026.01);
U.S. Cl.
CPC ...
H10D 84/83 (2025.01); H10D 84/0151 (2025.01); H10D 84/038 (2025.01); H10W 10/0143 (2026.01); H10W 10/0145 (2026.01); H10W 10/0148 (2026.01); H10W 10/17 (2026.01);
Abstract

A semiconductor device includes a first isolation structure extending through an upper portion of a substrate and defining a first active region, a first gate structure on the substrate, and first source/drain regions at upper portions of the first active region adjacent to the first gate structure. The first isolation structure includes an upper isolation pattern structure and a lower isolation pattern. The upper isolation pattern structure includes a first isolation pattern and a second isolation pattern covering a sidewall of the first isolation pattern. The lower isolation pattern is formed under and contacting the upper isolation pattern structure, and a width of the lower isolation pattern is greater than a width of the upper isolation pattern structure.


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