The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2026

Filed:

May. 26, 2023
Applicant:

Cambridge Gan Devices Limited, Cambridge, GB;

Inventors:

Florin Udrea, Cambridgeshire, GB;

Loizos Efthymiou, Cambridgeshire, GB;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/80 (2025.01); H10D 8/60 (2025.01); H10D 30/47 (2025.01); H10D 62/10 (2025.01); H10D 62/83 (2025.01); H10D 62/85 (2025.01); H10D 64/00 (2025.01);
U.S. Cl.
CPC ...
H10D 84/811 (2025.01); H10D 8/60 (2025.01); H10D 30/475 (2025.01); H10D 62/111 (2025.01); H10D 62/83 (2025.01); H10D 62/8503 (2025.01); H10D 64/111 (2025.01);
Abstract

A III-nitride power semiconductor device comprising a heterojunction transistor, the heterojunction transistor comprising: an active III-nitride semiconductor region comprising at least one heterojunction formed between a GaN layer and a AlGaN layer; a drain terminal operatively connected to the active III-nitride semiconductor region; a source terminal laterally spaced from the drain terminal and operatively connected to the active III-nitride semiconductor region; and a gate terminal positioned over the active III-nitride semiconductor region, the gate terminal being formed between the drain terminal and the source terminal. The power device further comprises a substrate, wherein the substrate comprises a monocrystalline silicon material; a high voltage diode associated with the substrate, the high voltage diode comprising a cathode terminal, an anode terminal and a drift region, wherein at least a part of the drift region is formed within substrate; wherein the heterojunction transistor is positioned over the substrate such that the high voltage diode is located below at least part of the heterojunction transistor, wherein the drift region and is adjacent to and in physical contact with the active III-nitride semiconductor region.


Find Patent Forward Citations

Loading…